A Delay Line Based Design-for-Test Technique for Sinusoidal Jitter Measurement
碩士 === 國立臺灣大學 === 電子工程學研究所 === 94 === In this thesis, an on-chip sinusoidal jitter extraction technique based on period tracking is presented. The proposed technique is a viable on-chip solution. It utilizes a variable delay line and a phase comparator to track the signal’s cycle lengths without ext...
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| Format: | Others |
| Language: | en_US |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/96074244147913428994 |
| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 94 === In this thesis, an on-chip sinusoidal jitter extraction technique based on period tracking is presented. The proposed technique is a viable on-chip solution. It utilizes a variable delay line and a phase comparator to track the signal’s cycle lengths without external reference. Digital signal processing techniques are then applied to the obtained signal period sequence to derive the amplitudes and frequencies of the sinusoidal jitter components. Numerical simulations are performed to validate the idea. The results show that the proposed approach can achieve high amplitude and frequency estimation accuracy and is robust in the presence of random jitter components and delay line variations.
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