A Delay Line Based Design-for-Test Technique for Sinusoidal Jitter Measurement

碩士 === 國立臺灣大學 === 電子工程學研究所 === 94 === In this thesis, an on-chip sinusoidal jitter extraction technique based on period tracking is presented. The proposed technique is a viable on-chip solution. It utilizes a variable delay line and a phase comparator to track the signal’s cycle lengths without ext...

Full description

Bibliographic Details
Main Authors:	Chia-Yuan Kuo, 郭嘉元
Other Authors:	黃俊郎
Format:	Others
Language:	en_US
Published:	2006
Online Access:	http://ndltd.ncl.edu.tw/handle/96074244147913428994

id	ndltd-TW-094NTU05428131
record_format	oai_dc
spelling	ndltd-TW-094NTU054281312015-12-16T04:38:40Z http://ndltd.ncl.edu.tw/handle/96074244147913428994 A Delay Line Based Design-for-Test Technique for Sinusoidal Jitter Measurement 以延遲線量測週期性抖動之可測試性技術 Chia-Yuan Kuo 郭嘉元碩士國立臺灣大學電子工程學研究所 94 In this thesis, an on-chip sinusoidal jitter extraction technique based on period tracking is presented. The proposed technique is a viable on-chip solution. It utilizes a variable delay line and a phase comparator to track the signal’s cycle lengths without external reference. Digital signal processing techniques are then applied to the obtained signal period sequence to derive the amplitudes and frequencies of the sinusoidal jitter components. Numerical simulations are performed to validate the idea. The results show that the proposed approach can achieve high amplitude and frequency estimation accuracy and is robust in the presence of random jitter components and delay line variations. 黃俊郎 2006 學位論文 ; thesis 44 en_US
collection	NDLTD
language	en_US
format	Others
sources	NDLTD
description	碩士 === 國立臺灣大學 === 電子工程學研究所 === 94 === In this thesis, an on-chip sinusoidal jitter extraction technique based on period tracking is presented. The proposed technique is a viable on-chip solution. It utilizes a variable delay line and a phase comparator to track the signal’s cycle lengths without external reference. Digital signal processing techniques are then applied to the obtained signal period sequence to derive the amplitudes and frequencies of the sinusoidal jitter components. Numerical simulations are performed to validate the idea. The results show that the proposed approach can achieve high amplitude and frequency estimation accuracy and is robust in the presence of random jitter components and delay line variations.
author2	黃俊郎
author_facet	黃俊郎 Chia-Yuan Kuo 郭嘉元
author	Chia-Yuan Kuo 郭嘉元
spellingShingle	Chia-Yuan Kuo 郭嘉元 A Delay Line Based Design-for-Test Technique for Sinusoidal Jitter Measurement
author_sort	Chia-Yuan Kuo
title	A Delay Line Based Design-for-Test Technique for Sinusoidal Jitter Measurement
title_short	A Delay Line Based Design-for-Test Technique for Sinusoidal Jitter Measurement
title_full	A Delay Line Based Design-for-Test Technique for Sinusoidal Jitter Measurement
title_fullStr	A Delay Line Based Design-for-Test Technique for Sinusoidal Jitter Measurement
title_full_unstemmed	A Delay Line Based Design-for-Test Technique for Sinusoidal Jitter Measurement
title_sort	delay line based design-for-test technique for sinusoidal jitter measurement
publishDate	2006
url	http://ndltd.ncl.edu.tw/handle/96074244147913428994
work_keys_str_mv	AT chiayuankuo adelaylinebaseddesignfortesttechniqueforsinusoidaljittermeasurement AT guōjiāyuán adelaylinebaseddesignfortesttechniqueforsinusoidaljittermeasurement AT chiayuankuo yǐyánchíxiànliàngcèzhōuqīxìngdǒudòngzhīkěcèshìxìngjìshù AT guōjiāyuán yǐyánchíxiànliàngcèzhōuqīxìngdǒudòngzhīkěcèshìxìngjìshù AT chiayuankuo delaylinebaseddesignfortesttechniqueforsinusoidaljittermeasurement AT guōjiāyuán delaylinebaseddesignfortesttechniqueforsinusoidaljittermeasurement
_version_	1718151126800400384

A Delay Line Based Design-for-Test Technique for Sinusoidal Jitter Measurement

Similar Items