| Summary: | 碩士 === 南台科技大學 === 電子工程系 === 94 === In recent years, studies about Surrounding-Gate (SG) transistor have successively been proposed, and have attracted a lot of attention. For future ULSI's design, it is shown that SG transistor have the following advantages, such as: reduced short channel effects (SCEs) effectively, high packing density, high-speed cut-off frequency, low-power consumption, the application of Stacked circuit design, the excellent gate control over the channel and reduced fringe-induced barrier lowering (FIBL) effectively. To make the device be applied to the simulation, it is necessary to develop an analytical 2D model to predict precisely the performance of the SG MOSFET.
In this thesis, based on fully closed-form solutions of Poisson’s equation in both regions of Si body and gate insulator, a physical and analytical model for undoped Surrounding-Gate (SG) MOSFETs has been derived. It uses the superposition method and simplifying assumptions of 2D boundary conditions to derive the model. The model shows the distribution of electric potential, short channel threshold voltage roll-off (ΔVTH), subthreshold current, subthreshold slope (Swing), drain-induced barrier lowering (DIBL) effects and FIBL effects arising from the use of high-k gate dielectric. The new model is verified by published numerical simulations with close agreement. It is found that the SCEs and FIBL effects for undoped SG MOSFETs can be effectively reduced by using both short channel length and high-k gate dielectric. Due to its computational efficiency, this model can be applied for SPICE simulation.
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