RLC Crosstalk analysis and parasitic capacitance modeling on VLSI interconnections

碩士 === 南台科技大學 === 電子工程系 === 94 === Continuous advancements in the field of very large scale integrated circuits and very high speed integrated circuits have resulted in smaller chip sizes, smaller device geometries, and millions of closely spaced interconnections in one or more levels that connect t...

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Bibliographic Details
Main Authors: Poan Tsai, 蔡柏安
Other Authors: T. K. Chiang
Format: Others
Language:en_US
Published: 2006
Online Access:http://ndltd.ncl.edu.tw/handle/25125182969662680500