RLC Crosstalk analysis and parasitic capacitance modeling on VLSI interconnections
碩士 === 南台科技大學 === 電子工程系 === 94 === Continuous advancements in the field of very large scale integrated circuits and very high speed integrated circuits have resulted in smaller chip sizes, smaller device geometries, and millions of closely spaced interconnections in one or more levels that connect t...
Main Authors: | Poan Tsai, 蔡柏安 |
---|---|
Other Authors: | T. K. Chiang |
Format: | Others |
Language: | en_US |
Published: |
2006
|
Online Access: | http://ndltd.ncl.edu.tw/handle/25125182969662680500 |
Similar Items
-
Design of high-performance VLSI RLC interconnects
by: Awwad, Falah Rashad
Published: (2002) -
Crosstalk Estimation for Coupled RLC Interconnects by Sensitivity Computation Based on Pole-zero Analysis
by: Hou-Yi Hung, et al.
Published: (2007) -
VLSI Interconnect Capacitance Characterization
by: Wen-Hsiang Chou, et al.
Published: (2004) -
Interconnection Crosstalk Minimization In Submicro VLSI Design
by: Xie, Wu-Jian, et al.
Published: (1998) -
Interconnection Crosstalk Minimization In Submicro VLSI Design
by: Shieh, Wu-Chien, et al.
Published: (1998)