| Summary: | 碩士 === 國立臺北科技大學 === 電腦與通訊研究所 === 94 === In this thesis, we propose a new VLSI architecture for low-power turbo decoder. This architecture includes three parts to improve power dissipation properties. Firstly, we propose a new adaptive iteration algorithm that can employ extrinsic information character to avoid unnecessary iterations. Secondly, we develop a hybrid architecture for the SISO decoder which decreases the state storage space and power consumption. Finally, we propose a new normalization technique which can reduce the state metric calculation without decoding performance loss. We also use Xilinx Vertix-4 FPGA to verify this new adaptive turbo decoder. Experiments show that we gets 2.2~12.2％ memory bits size and 9.3~15.5％ memory area saving in comparison with other stopping iteration algorithms. In our SISO decoder, we can save 42~54% memory bits size and 23~40％ memory area. In state metric normalization, we can save 43.8~89.4％ power consumption in our architecture. Finally, we have designed this new adaptive turbo decoder by TSMC .18μm 1P6M process. When operation frequency is 97.5MHz, the throughput of this decoder is 7.88~23.64Mbps, and chip size including I/O PAD is 2.14x2.14mm2 .
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