A 10-BIT 5-MS/S LOW-VOLTAGE PIPELINE ADC
碩士 === 大同大學 === 電機工程學系(所) === 94 === In this thesis, we design a 10-bits 5 Msample/s low-voltage pipeline ADC. Because the threshold voltage of transistors does not scale with the technology, circuits used in the pipeline ADC in the past could not obtain the desired dynamic range in low voltage. Sev...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/08117410140618267663 |