The Research of Very-High-Speed Fully Differential CMOS Sample-and-Hold Circuit with Low Hold Pedestal
碩士 === 國立雲林科技大學 === 電子與資訊工程研究所 === 94 === A new technique for realizing a very-high-speed low-power low-voltage fully differential CMOS sample-and-hold circuit with low hold pedestal is presented. To achieve high sampling linearity the circuit utilizes linearized input switches. The fully differenti...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/20229770108912700812 |