An Adjustable Pulsewidth of High Speed Digital Pulsewidth Locked Loop
碩士 === 國立雲林科技大學 === 電子與資訊工程研究所 === 94 === This thesis proposed a new circuit architecture that solves the pulse-width quality problem of the high-speed digital-system-chip clock signal. From pervious studies, high-speed pulse-width control can divide into two kinds of circuit structures. Firstly, t...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/57256765861483334592 |