A New High Performance Low Power Low Cost Viterbi Decoder Using Automatic Bit Reset Technique
碩士 === 國立雲林科技大學 === 電子與資訊工程研究所 === 94 === We design a new high-speed low-power and low-cost Viterbi Decoder(VD) that is often applied to the decoding of the well-known convolutional code. We investigate how to decline the adder bits in the ACS﹙Adder Compare Select﹚unit and propose a normalization te...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/56336947640269076264 |