A New High Performance Low Power Low Cost Viterbi Decoder Using Automatic Bit Reset Technique

• Main Authors: Yi-Ze Lai, 賴義澤
• Other Authors: Po-Hui Yang
• Format: Others
• Language: zh-TW
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/56336947640269076264

碩士 === 國立雲林科技大學 === 電子與資訊工程研究所 === 94 === We design a new high-speed low-power and low-cost Viterbi Decoder(VD) that is often applied to the decoding of the well-known convolutional code. We investigate how to decline the adder bits in the ACS﹙Adder Compare Select﹚unit and propose a normalization technique to target the improvement in speed power and area. Finally, we utilize pipeline to operate and reach the result again. After we verified the function and made the platform by FPGA, we also used UMC 0.18μm 1.8V 1P6M Standard Cell Library to implement it. This thesis uses our new normalization circuit to reduce the data bits in ACS unit. We propose a new-type AS-C﹙Adder Select -Compare﹚pipeline structure to balance the delay time of each unit in order to realize the high speed pipeline operation. This new structure was verified by a FPGA platform. With implementation by using UMC 0.18μm 1.8V Standard Cell Library, the proposed VD can improve the data rate up to 3Gbps for decoding a (3,1,2) convolutional code. To compare with the traditional VD[13], the proposed VD is improved by 500% in decoding speed and is reduced by 60% in power consumption. Furthermore, the chip area of the new VD is reduced by 45% as compared to the traditional one. The speed of operation of the proposed VD is up to 1GHz. Under 1GHz operation, the proposed VD consumes 15.7mW in power and the area of chip is about 130μm*130μm.