Using Essential Inverters for Interconnect Delay Reduction
碩士 === 元智大學 === 資訊工程學系 === 94 === With the advance of VLSI process technology, interconnect delay increasely dominates the circuit performance. Buffer insertion is one of the crucial approaches to this problem. However, buffer insertion not only increases total chip area but also increases power dis...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2006
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/55630463666515434990 |