Test Time and Test Power Reduction for Multi-Scan Circuits based on Scan Cell Reordering
碩士 === 元智大學 === 資訊工程學系 === 94 === When the process of very large-scale integrated circuits scales down into deep sub-micron, the complexity of circuit designs is greatly increased. So, there are two problems in the IC (Integrated Circuit) testing: First, the circuit in test mode consumes more power...
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| Format: | Others |
| Language: | en_US |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/48383675096971972606 |