A Methodology of Designing Standard Cells to Facilitate Redundant-Via Insertion
碩士 === 元智大學 === 資訊工程學系 === 94 === In the layout design, a via connects two or more wire segments of different metal layers. With device and interconnect width keep shrinking, process variation may cause via failure in manufacturing. A failed via can increase the resistance of a net and cause timing...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/19647008928069560415 |