Timing-Driven Steiner Tree Construction with Wire Sizing, Buffer Insertion and Obstacle Avoidance
碩士 === 中華大學 === 資訊工程學系(所) === 95 === As VLSI technology enters deep submicron era, interconnect delay becomes a dominant factor in determining circuit performance. As the timing delay of the interconnect nets has become more important in performance-driven design, Steiner tree algorithms have focuse...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Online Access: | http://ndltd.ncl.edu.tw/handle/17785658271921944464 |