| Summary: | 碩士 === 中華大學 === 資訊工程學系(所) === 95 === As VLSI technology enters deep submicron era, interconnect delay becomes a dominant factor in determining circuit performance. As the timing delay of the interconnect nets has become more important in performance-driven design, Steiner tree algorithms have focused on minimizing the timing delay of the interconnect net. In this paper, given a set of connecting nodes in a signal net, based on the concept of sharing-buffer insertion and hidden Steiner-point assignment and the result of optimal wire width and buffer insertion in a wire segment[7], a top-down-based merging approach is proposed to construct a timing-driven rectilinear Steiner tree with wire sizing， buffer insertion，and obstacle avoidance. The experimental results show that our proposed merging approach without wire sizing， buffer insertion， and obstacle avoidance reduces 5%~30% timing delay than MVERT approach[17] in reasonable CPU time. Besides that, the proposed approach with wire sizing and buffer insertion reduces 28%~76% timing delay than that without wire sizing and buffer insertion for the tested signal nets. The experimental results also show that our timing-driven rectilinear Steiner tree with wire sizing， buffer insertion，and obstacle avoidance approach obtains better timing-driven Steiner trees than FAST-RTBW approach[11] for the tested signal nets.
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