Design of a 10-bit 50MHz Pipelined Analog-to-Digital Converter
碩士 === 崑山科技大學 === 電子工程研究所 === 95 === In this thesis, we design a 10-bit 50MHz pipelined analog-to-digital converter (ADC) by TSMC 0.35�慆 2P4M mixed signal process technology. The supply voltage is 3.3V. The ADC architecture is nine stage pipelined ADC in this design. In formal we adopt 1.5-bit/per s...
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| Format: | Others |
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2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/63562885702621629198 |