Design of Dual-Path Low Density Parity Check Code Decoder
碩士 === 國立中興大學 === 電機工程學系所 === 95 === In this thesis, a high throughput decoder for Low Density Parity Check Code is presented. The (500, 1500) check matrix is a random and regular matrix whose column weight and row weight are 3 and 9, respectively. The design includes 4 units, which are Variable Nod...
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| Format: | Others |
| Language: | zh-TW |
| Online Access: | http://ndltd.ncl.edu.tw/handle/00082499138906823504 |