| Summary: | 碩士 === 國立中興大學 === 電機工程學系所 === 95 === In this thesis, a high throughput decoder for Low Density Parity Check Code is presented. The (500, 1500) check matrix is a random and regular matrix whose column weight and row weight are 3 and 9, respectively. The design includes 4 units, which are Variable Node Unit (VNU), Check Node Unit (CNU), Memory Unit and Distributor. The Memory Unit is composed of Artisan 2-Ports Register File. The size of the Register File was reduced greatly by appropriate arrangement. The Min-sum algorithm was applied in CNU.
During the decoding process, CNU and VNU operations are active alternatively in every decoding iteration. To increase the throughput, these idled CNU or VNU circuit blocks can be used to process another codeword, thus, the throughout is increased to almost two times. Moreover, if pipelined architectures are applied to both VNU and CNU, the clock rate cnn be increased, which makes 2.5 times the throughput of the original one.
In this thesis, the design was synthesized using TSMC 0.18 μm CMOS technology. It can achieve 3.79 Gbps throughput with 8 iterations in 9.78 M(μm2) cell area. The power dissipation is 2204 mW at clock frequency of 166MHz..
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