Study on the Reliability of P Channel Poly-Silicon Thin Film Transistors

• Main Authors: Wei-Chun Chang, 張為鈞
• Other Authors: Han-Wen Liu
• Format: Others
• Language: en_US
• Online Access: http://ndltd.ncl.edu.tw/handle/32549097390574587157

碩士 === 中興大學 === 電機工程學系所 === 95 === Poly-Si TFTs has been widely used recently, and nowadays, the reliability of TFTs plays an important role. When poly-Si TFTs are applied to the flat panel displays, the TFTs is driven by AC signal. Therefore, the reliability test is not only focus on DC bias stress, the instability of TFTs under AC stress also becomes important now. In this thesis, we study the reliability of the p-channel TFTs by (1) bias temperature stress (BTS), and (2) alternating current (AC) bias stress. For BTS, we use TFTs with three different channel lengths to realize the BTS. We apply a hot chuck to control the temperature and constant voltage on the gate and drain. We find that the shorter the channel length is, the more serious degradation will occur; and we also observe that the TFTs with the same channel length, the higher temperature we apply, the larger damage on TFTs will occur. In addition, the “turn-over” behavior will appear in the degradation of electrical characteristic, and it depends on the channel length and the temperature we apply. Besides I-V measurement, we also measure the C-V characteristics. We discover that after BTS, the location of degradation is mainly near the source end of TFTs. For AC stress, we use TFTs with the same dimension, and we apply synchronous and asynchronous AC gate signal and drain signal. Under synchronous AC gate and drain bias stress, the lower frequency of AC signal will cause a more serious degradation. And under asynchronous AC gate and drain bias stress, we choose a specific frequency that would cause the largest damage on TFTs from above experiments. We find that under not only drain signal delay stress but also gate signal delay stress, the larger delay portions will cause the larger damage on TFTs