Design of a Simple Pulse Width Control Loop Circuit by Using Digital Frequency Dividers

• Main Authors: Chi-Ching Chen, 陳基清
• Other Authors: Soon-Jyh Chang
• Format: Others
• Language: zh-TW
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/16523484272909484881

碩士 === 國立成功大學 === 電機工程學系碩博士班 === 95 === Most digital and mixed-signal circuits use a lot of clock signals to trigger a periodic notification at the requested time. The accuracies on frequencies, phases and pulse widths of clock signals are very important for high speed applications. For the issues of adjustment on frequency and phase of a signal, current phase locked loop (PLL) and delay locked loop (DLL) technologies have achieved good results in recent years. For the topics of pulse width control for a given signal, many good research results have been presented to deal with the specific case of balanced duty cycle (duty cycle is 50%). However, on the subject of unbalanced duty cycle (duty cycle is not 50%) adjustment, current design must employ many extra current sources and switches to accomplish duty cycle adjustment. Such a method raises the chip area, power consumption and design complexity, and consequently increases the cost. This thesis proposes an alternative method which can regulate duty cycle of a periodic signal. In this thesis, we first survey recently published design of pulse width control loop circuits, and analyze the advantages and challenges of each method. Secondly, we modify the traditional PWCL circuit by using a simple frequency divider to achieve the goal of duty cycle regulation. The experimental results show that the duty cycle can be correctly adjusted to 50%, 33% (67%), and the proposed design has advantages of small chip area and low power consumption. Finally, we analyze this circuit performance and present an improvement method for different frequencies and duty cycles All major function blocks proposed in this thesis are all verified and simulated with TSMC 0.35�慆 2P4M CMOS process. The experimental results show a good agreement with the analysis.