A Heuristic Multi-Supply Voltage Assignment for Logical Circuits with Built-in Timing and Power Analysis
碩士 === 國立成功大學 === 電機工程學系碩博士班 === 95 === The majority of power consumption in CMOS digital circuits is dynamic power. According to the formula of dynamic power consumption, one of the most effective techniques to reduce power consumption is supply voltage reduction. However, reducing supply voltage w...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/48408578243667199834 |