An ADPLL Clock Generator with Large Frequency Multiplication Factor for Video Application
碩士 === 國立交通大學 === 電機學院碩士在職專班電子與光電組 === 95 === In this thesis, an all-digital phase-locked loop with large multiplication factor is presented. This circuit can be applied to the video system as a clock generator. It receives the horizontal synchronous signal from the graphics card and then generates...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/47484094175765669069 |