| Summary: | 碩士 === 國立交通大學 === 電機學院IC設計產業專班 === 95 === This thesis focuses on the ESD protection design for high-speed input/output (I/O) interface circuit. The gate oxide of the MOSFET transistor becomes thinner as the CMOS technology scales, which enables the high-speed I/O interface circuits with higher operating frequency. Unfortunately, there exists a challenge to design an ESD protection circuit with satisfactory ESD robustness and low parasitic effects to the gigahertz high-speed I/O circuit. This thesis presents a design methodology to design the ESD protection circuit for gigahertz high-speed I/O circuits with high ESD robustness and low parasitic capacitance.
There are two major designs in this thesis, in first part, the two-port ground-signal-ground (GSG) measurement setup in the radio-frequency band (~GHz) is used to measure the high-frequency characteristics of ESD devices and the TLP measurement system is used to measure the ESD robustness of the ESD devices in a 0.13-�慆 CMOS process. Therefore, the relationship between the high-frequency characteristics and ESD robustness under different ESD device dimensions can be obtained.
The second part presents the most suitable ESD device for gigahertz high-speed applications based on the database which had been established in the first part. With the database, the optimal ESD device dimensions can be obtained as long as the requirement of parasitic capacitance and ESD robustness are determined. Besides, placing the ESD protection device under the bond pad can further reduce the parasitic capacitance and the total chip area.
The test devices and the ESD protection design in this thesis have been fabricated in a 0.13-�慆 CMOS process, and the experimental results have shown that this ESD protection design is suitable for gigahertz high-speed I/O interface circuits.
|
|---|
