The Study of Vertical Channel Low Temperature Polycrystalline Silicon Thin-Film Transistors Fabricated by Ni –Silicide Induced Lateral Crystallization Technology

碩士 === 國立交通大學 === 電子工程系所 === 95 === ABSTRACT In this thesis, we first study about horizontal channel poly crystalline thin film transistors by metal induced lateral crystallization (MILC). It is known that nickel deposition on source and drain regions cause metal contaminations on these regions aft...

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Bibliographic Details
Main Authors: Jiou-Teng Lai, 賴久騰
Other Authors: Tan-Fu Lei
Format: Others
Language:en_US
Published: 2007
Online Access:http://ndltd.ncl.edu.tw/handle/56566905124041369558
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Summary:碩士 === 國立交通大學 === 電子工程系所 === 95 === ABSTRACT In this thesis, we first study about horizontal channel poly crystalline thin film transistors by metal induced lateral crystallization (MILC). It is known that nickel deposition on source and drain regions cause metal contaminations on these regions after the MILC process. Thus we use nickel deposition on offset regions of metal to complete the MILC process. Because the result of the experiment shows that the field effective mobility has no remote effect after the MILC process even though the sub-threshold swing and leakage are reduced effectively, we infer that the a-Si channel film has be transferred to poly-Si during the deposit of a-Si gate rather than the MILC process. Thus in the next part of the thesis, the device structure is changed: the structure would be based on button gate thin film transistors, which would keep a-Si channel due to it is deposited after poly Si gate. With the vertical channel poly crystalline thin film transistors, the idea based on button gate structure thin film transistors, the vertical channel length is defined by gate electrode height rather than lithography technology. We can then fabricate this device, which has shorter channel size by lithography machine (G-Line stepper), and the source/drain regions is the same as the traditional top gate thin film transistors defined at both sides of the gate. When the source/drain implants, the floating N+(P+) region is formed on the gate electrode because of the design positions of source, drain and channel regions. We will further discuss the influence of this floating region as well as how this vertical structure is equivalent the dual gate thin film transistor due to the arrangement of electrodes. We hope that it can induce the gate’s controllability and reduce the short channel effect The study of vertical channel with high field effect mobility by Ni induced lateral crystallization, which can form larger grains on channel regions and reduce grain boundary defects. We detect the method of Ni induced lateral crystallization through high field effective mobility, but that accumulates too much Ni on floating N+ (P+) region and causes defects and metal contamination. As Ni is used to form silicde and then proceed to low temperature annealing, we can observe the floating region that has no Ni acumination regions or contaminations. This aids us in obtaining good electronic performance of this device, not only the remote field effective mobility but also the vast improvement of sub-threshold swing and on/off currents.