Impacts of a Buffer Layer and Hi-wafers on the Performance of Strained-channel NMOSFETs with SiN Capping Layer

• Main Authors: Tzu-I Tsai, 蔡子儀
• Other Authors: Tiao-Yuan Huan
• Format: Others
• Language: zh-TW
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/73745391359072300590

碩士 === 國立交通大學 === 電子工程系所 === 95 === In this thesis, the effects of both the Si3N4 layer capping over the gate and the hydrogen-blocked TEOS buffer layer inserted prior to the Si3N4 deposition, on the NMOS device characteristics as well as the correlative hot-electron degradation were investigated. The devices were built on two kinds of the substrates, namely, Cz and Hi-wafers. Besides, the influences of the F channel implant on both fundamental performance and the related reliability of the fabricated devices were also explored. For devices on the Hi-wafer, the buffer layer would not degrade the device performance. On the contrary, the buffer layer for devices built on Cz wafers would degrade the performance. Such disparity is attributed to the better surface quality of the Hi wafers. On the other hand, the F channel implant draws significant impacts on the device performance for devices built on Cz wafers, such as degradation of Gm and S.S. When Hi wafers were used as the starting substrates, such negative impacts could be relaxed. These findings highlight the merits of Hi wafers over that of Cz wafers. The thermal budget associated with the deposition of the Si3N4 capping layer could help redistribute the segregated boron dopants in the channel and alleviate the reverse short-channel effect, although the poly-depletion effect becomes worse. More importantly, we found that hydrogen species is the primary culprit for aggravated reliabilities in strained devices. The TEOS buffer layer could effectively block the diffusion of hydrogen species from Si3N4 into the channel and interface of Si/SiO2 during the Si3N4 deposition and subsequent thermal cycles. The hot-electron degradation is adversely affected when the Si3N4 capping layer is deposited over the gate as compared with the control samples, regardless of the types of wafers. When a TEOS buffer layer was inserted prior to the Si3N4 deposition, although still worse than the control ones, significant improvement in resistance to the hot-carrier degradation over that without buffer is achieved. Besides, with the assistance of the F channel implant, the hot-carrier degradation of devices is obviously improved.