On Power-State-Aware Routing and Buffer Insertion
碩士 === 國立交通大學 === 電子工程系所 === 95 === Interconnect delay and low power are two of the main issues in nanotechnology. Buffer insertion during routing can reduce interconnect delay; power state management and multiple supply voltage can lower power consumption. However, buffering without considering pow...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/16464217644546359321 |