The Analytical Models and Optimization Designs for VLSI Interconnection

博士 === 國立交通大學 === 電子工程系所 === 95 === Increasing complexity in very large scale integration (VLSI) circuits makes metal interconnection a significant factor affecting circuit performance. The dramatically increased amount of interconnection line in chip makes the interconnect delay and crosstalk noise...

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Bibliographic Details
Main Authors: Trent Gwo-Yann Lee, 李國晏
Other Authors: Tseung-Yuen Tseng
Format: Others
Language:zh-TW
Online Access:http://ndltd.ncl.edu.tw/handle/51026035425971785424