A 3.125GHz Half-rate Clock and Data Recovery for 10GBASE-LX4
碩士 === 國立交通大學 === 電信工程系所 === 95 === The purpose of this paper is to implement a 3.125GHZ clock and data recovery circuit (CDR) for 10GBASE-LX4 by using TSMC 0.18um process. The structure of the CDR belongs to the phase locked loop. It consists of phase detector, charge pump, loop filter, and VCO. Th...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2007
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/00171090138612997606 |