Spurious Suppressing Design for UWB Synthesizers
碩士 === 國立交通大學 === 電信工程系所 === 95 === This thesis presents a CMOS frequency synthesizer with an efficient algorithm for in-band spurious suppression by using the divide-by-two circuit after the mixer. An implementation example had been developed with UWB Synthesizer from 3.1-GHz to 6.3-GHz as the test...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2007
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/95718883035725181180 |