Multi-Symbol Codec for H.263 and the Synthesizable Verilog Code Generator Thereof
碩士 === 國立中山大學 === 電機工程學系研究所 === 95 === The first topic of this thesis is to carry out a multi-symbol codec (encoder-decoder) design for interfacing variable-length and fixed-length data conversion of H.263. The poor memory efficient of the variable-length can be avoided while its advantages can be r...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/5ug37d |