Topology generation for gated and buffered clock tree
碩士 === 國立清華大學 === 資訊工程學系 === 95 === Clock networks aect the performance and property of VLSI circuits greatly. Power reduction issue for the clock network becomes an active research area since a large portion of power is dissipated on clock networks. Clock gating is an eective power reduction techni...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/76550974519150344736 |