Detection of stress-induced Interface Traps and Border Traps in MOSFETs with High-K Gate Dielectrics
碩士 === 國立清華大學 === 工程與系統科學系 === 95 === Abstract To fulfill the scaling scenario as projected in the International Technology Roadmap for Semiconductors (ITRS), it is widely believed that a high-k (high permittivity) dielectric is needed to replace SiO2 as the CMOS gate dielectric to reduce signif...
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| Format: | Others |
| Language: | en_US |
| Published: |
2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/35641987665485802149 |