A Dual Mode Phase Locked Loops with low jitter LC-VCO for 2.56/3.2 Gbps SERDES
碩士 === 國立清華大學 === 通訊工程研究所 === 95 === In many circuits, PLL “Phase Locked Loops” plays an important role in an output high speed clock to follow the slow input clock. Examples of application that uses PLL include clock and data recovery, delay locked loops, clock synthesis, and synchronization. In th...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/44063540603862137290 |