Two-Terminal Nets Routing Algorithms on Printed Circuit Boards

• Main Authors: Fang-Cheng Kuo, 郭芳誠
• Other Authors: Gene-Eu Jan
• Format: Others
• Language: zh-TW
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/73193763203410070685

碩士 === 國立臺北大學 === 通訊工程研究所 === 97 === In the physical design cycle for very large scale integration (VLSI), there is several stage should be discussed such as partitioning, floor planning & placement, routing, compaction, extraction & verification. The part of routing is one of the major issue should be discussed for Electronic Design Automation (EDA).A quality routing plan will reduce actual cost in area and total metal length for VLSI and Printed circuit board (PCB). There are three common architectures for PCB: single Layer, Double Layer PCB, and Multi Layer. Single Layer PCB is fundamental of the others. In this article, we applied the lengths and number of intersections based on High Geometry Maze Router to find the order for each two-terminal net. The two reordering policy in the fast single-layer two-terminal nets routing algorithm to obtain a heuristic solution with reasonable lengths of nets. The space and time complexities are O(N) and O(pN), respectively, where N is the number of elements in the 2-D matrix and p is the number of two-terminal pairs. In order to avoid the continual terminals , we discuss two preprocess for observable pattern in PCB.