A Rapid Simulation Environment for Application Performance Estimation on Parameterized Multi-core/Multi-threading Architecture Models
碩士 === 國立臺灣大學 === 資訊工程學研究所 === 95 === The technique of increasing clock rate to speed up the application performance have reached bottlenecks such as power dissipation, design complexity, and diminishing returns from increasing Instruction Level Parallelism (ILP) supportcite{LDMoore}. Therefore, com...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/40643131696484075030 |