| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 95 === According to International Technology Roadmap for Semiconductors (ITRS), the interconnection complexity has increased and dominated the SoC design and its performance. By the end of the decade, the popular bus-based SoC communication will meet its bottleneck in the deep-submicron environment. Recently, researches on On-Chip Network (OCN) have been actively discussed to solve the problem of on chip bus.
In this thesis, we proposed a design concept of On-Chip Networking system (OCN system). The OCN system designed according to this concept is called traffic-aware OCN system. The traffic-aware OCN system should be hardware-efficient in already known traffic case and can dynamically adjust for better system performance at run time.
For hardware efficiency issue, we have built a variety of routing engines in the HW library and formed a hardware reduction flow. According to the already known traffic on the chip, we can choose the most suitable routing engine at each node of the network. The proposed dynamically adjustable buffer allocation can increase the buffer utilization and therefore can reach the same performance with less hardware overhead.
For better system performance under unpredictable traffic, the proposed traffic-aware scheduling can lower the packet latency and increase system throughput by reducing congestion rate and increasing bandwidth utilization. The RTL simulation shows the OCN system with traffic-aware scheduling performs better than the generic OCN system under uniform random traffic and hotspot traffic. The hardware overhead of traffic-aware technique is merely 6.9%.
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