| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 95 === As the IC fabrication technology advances, the transistor feature size keeps shrinking and it is possible now to integrate a complete system on a chip. However, as the device size decreases, the inevitable process variations become an important factor of manufacturing yield. Under the influence of process variations, the performances of the fabricated IC''s deviate from those of the nominal design. As a result, some IC''s may still function, but their specifications are out of the acceptable range. Monte Carlo simulation is a commonly used technique for yield estimation. Given the process variation distribution, a sufficient large number of circuit instances are generated to match the fabrication distribution. Then, all the generated instances are simulated. Then, one can predict the performance distribution and yield based on the simulation results. The problem with Monte Carlo simulation is the required long circuit simulation time.
Macromodel is a commonly used technique to speed up circuit simulation. The idea is to replace a circuit block, e.g., OPAMP, with a reduced model. However, for yield estimation applications, the macro-modeling process has to be performed for each circuit block instance because they are different in the existence of process variations. In this thesis, we propose a macromodel technique which is specially useful for yield estimation applications where a large number of macromodels have to be generated for the same circuit block.
We use a flash ADC to validate our technique, with the proposed macromodeling technique, the speed up of yield estimation is about 3.7 times, the speed up of circuit simulation is 4 times, and the pass/fail classification accuracy is about 94.17%.
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