A Fully Digital External Calibration Technique for 1-bit/stage Pipelined ADC
碩士 === 國立臺灣大學 === 電子工程學研究所 === 95 === In this thesis, a fully digital calibration scheme for the 1-bit/stage pipelined ADC is presented. It is extended from the existing digital calibration algorithm that still suffers arbitrary large DNL in some output codes. The proposed technique extracts these c...
Main Authors: | Yuan-Chi Yu, 游源祺 |
---|---|
Other Authors: | 黃俊郎 |
Format: | Others |
Language: | en_US |
Published: |
2007
|
Online Access: | http://ndltd.ncl.edu.tw/handle/75115747664456464992 |
Similar Items
-
DIGITAL CALIBRATION AND PREDICTION OF EFFECTIVE NUMBER OF BITS FOR PIPELINE ADC
Published: (2013) -
The Design and Realization of Digital Calibration in 10-bit 10 MSPS Pipelined ADC
by: Shan-Chun Hwang, et al.
Published: (2001) -
A Novel Digital Background Calibration Technique for 16 bit SHA-less Multibit Pipelined ADC
by: Swina Narula, et al.
Published: (2016-01-01) -
A 12-BIT 50-MS/S BUILT-IN ANALOG SELF-CALIBRATED PIPELINE ADC
by: Yu-Chen Shen, et al.
Published: (2006) -
Feasibility of a 16bit, 3MSPS multibit per stage pipeline ADC using digital calibration
by: Courcy, Matthew Louis, 1973-
Published: (2010)