Multilevel Gridless Full-Chip Routing Considering Performance and Manufacturability
博士 === 臺灣大學 === 電子工程學研究所 === 95 === As technology advances into the nanometer era, chips may consist of billions of transistors, and process geometries shrink to 90 nm and below. Further, the minimum feature size becomes significantly smaller than the lithographic wavelength, and thus design shapes...
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| Format: | Others |
| Language: | en_US |
| Published: |
2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/61661874567595696640 |