PLL and Pipelined Analog-to-Digital Converter for Communication Systems
碩士 === 國立臺灣科技大學 === 電子工程系 === 95 === This thesis presents chips for communication systems, including the phase-locked loop, its application to the clock and data recovery circuit, and its application to the pipelined ADC. The first chip is a design of phase-locked loop for the radio frequency transc...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2007
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/t4ah77 |