A Digital Pulse Width Modulator with Complementary Delay Lines
碩士 === 國立臺灣科技大學 === 電子工程系 === 95 === This research focuses on the design of key component,“Complementary Half Delay-Line(CHDL). ”It will significantly improve the practicability under the superiority of extremely low cost and stable. Delay-Locked Loops (DLLs) have been widely used for clock deskew i...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/33963062046163852090 |