| Summary: | 碩士 === 國立臺灣科技大學 === 電子工程系 === 95 === This research focuses on the design of key component,“Complementary Half Delay-Line(CHDL). ”It will significantly improve the practicability under the superiority of extremely low cost and stable.
Delay-Locked Loops (DLLs) have been widely used for clock deskew in stead of Phase-Locked Loop (PLLs) because of easy design and inherent stable. In nowadays, more and more applications, such as dram and clock generator where only used with PLLs in the past and are employed DLLs. So, the DLLs will be more significant in the near future. This research proposes a new structure is DLLs use in DPWM.
The main object of this research is the description and discussion in DPWM and DLLs, uses TSMC 0.35μm 2P4M CMOS process to design a DPWM and the supply voltage is 3.3V. The proposed DPWM resolution is 9.8ns and the similar first order curvature correction error is less than 0.3% in 400 KHz operation frequency. The chip area is merely 0.9*0.41 μm mm2
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