A Digital Pulse Width Modulator with Complementary Delay Lines

碩士 === 國立臺灣科技大學 === 電子工程系 === 95 === This research focuses on the design of key component,“Complementary Half Delay-Line(CHDL). ”It will significantly improve the practicability under the superiority of extremely low cost and stable. Delay-Locked Loops (DLLs) have been widely used for clock deskew i...

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Bibliographic Details
Main Authors:	Chun-Yan Chu, 朱俊彥
Other Authors:	Poki Chen
Format:	Others
Language:	zh-TW
Published:	2007
Online Access:	http://ndltd.ncl.edu.tw/handle/33963062046163852090

id	ndltd-TW-095NTUS5428046
record_format	oai_dc
spelling	ndltd-TW-095NTUS54280462015-10-13T14:16:32Z http://ndltd.ncl.edu.tw/handle/33963062046163852090 A Digital Pulse Width Modulator with Complementary Delay Lines 使用互補延遲線之數位脈波寬度調變器 Chun-Yan Chu 朱俊彥碩士國立臺灣科技大學電子工程系 95 This research focuses on the design of key component,“Complementary Half Delay-Line(CHDL). ”It will significantly improve the practicability under the superiority of extremely low cost and stable. Delay-Locked Loops (DLLs) have been widely used for clock deskew in stead of Phase-Locked Loop (PLLs) because of easy design and inherent stable. In nowadays, more and more applications, such as dram and clock generator where only used with PLLs in the past and are employed DLLs. So, the DLLs will be more significant in the near future. This research proposes a new structure is DLLs use in DPWM. The main object of this research is the description and discussion in DPWM and DLLs, uses TSMC 0.35μm 2P4M CMOS process to design a DPWM and the supply voltage is 3.3V. The proposed DPWM resolution is 9.8ns and the similar first order curvature correction error is less than 0.3% in 400 KHz operation frequency. The chip area is merely 0.9*0.41 μm mm2 Poki Chen 陳伯奇 2007 學位論文 ; thesis 92 zh-TW
collection	NDLTD
language	zh-TW
format	Others
sources	NDLTD
description	碩士 === 國立臺灣科技大學 === 電子工程系 === 95 === This research focuses on the design of key component,“Complementary Half Delay-Line(CHDL). ”It will significantly improve the practicability under the superiority of extremely low cost and stable. Delay-Locked Loops (DLLs) have been widely used for clock deskew in stead of Phase-Locked Loop (PLLs) because of easy design and inherent stable. In nowadays, more and more applications, such as dram and clock generator where only used with PLLs in the past and are employed DLLs. So, the DLLs will be more significant in the near future. This research proposes a new structure is DLLs use in DPWM. The main object of this research is the description and discussion in DPWM and DLLs, uses TSMC 0.35μm 2P4M CMOS process to design a DPWM and the supply voltage is 3.3V. The proposed DPWM resolution is 9.8ns and the similar first order curvature correction error is less than 0.3% in 400 KHz operation frequency. The chip area is merely 0.9*0.41 μm mm2
author2	Poki Chen
author_facet	Poki Chen Chun-Yan Chu 朱俊彥
author	Chun-Yan Chu 朱俊彥
spellingShingle	Chun-Yan Chu 朱俊彥 A Digital Pulse Width Modulator with Complementary Delay Lines
author_sort	Chun-Yan Chu
title	A Digital Pulse Width Modulator with Complementary Delay Lines
title_short	A Digital Pulse Width Modulator with Complementary Delay Lines
title_full	A Digital Pulse Width Modulator with Complementary Delay Lines
title_fullStr	A Digital Pulse Width Modulator with Complementary Delay Lines
title_full_unstemmed	A Digital Pulse Width Modulator with Complementary Delay Lines
title_sort	digital pulse width modulator with complementary delay lines
publishDate	2007
url	http://ndltd.ncl.edu.tw/handle/33963062046163852090
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A Digital Pulse Width Modulator with Complementary Delay Lines

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