Adaptive-Bandwidth and two different delay feedbacks phase-locked loop
碩士 === 南台科技大學 === 電子工程系 === 95 === The phase-locked loop (PLL) is a key component used broadly in various integrated circuit fields in recent years. It is generally used as clock generation in VLSI or frequency synthesizer in communication systems. Fast locking time, low jitter performance and low p...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/35794037742197493908 |