Chip Design for LDPC decoder employing New Log Domain Algorithm
碩士 === 國立臺北科技大學 === 電子電腦與通訊產業研發碩士專班 === 95 === In this thesis ,we propose a new VLSI architecture for high speed Low Density Parity Check Code decode. A new log domain algorithm is developed for LDPC decoding without losing error correction performance. In comparison with traditional LDPC, this algo...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/zcj3h6 |