| Summary: | 碩士 === 國立臺北科技大學 === 電子電腦與通訊產業研發碩士專班 === 95 === In this thesis ,we propose a new VLSI architecture for high speed Low Density Parity Check Code decode. A new log domain algorithm is developed for LDPC decoding without losing error correction performance. In comparison with traditional LDPC, this algorithm can decode the LDPC without saving and reading the value. Thus, we can simplify the decoding flow and increase the decoding throughput. For hardware implementation, we use Xilinx Vertix-4 FPGA to verify this new LDPC decoder firstly. Then we also design this chip by standard cell-based flow. Experiments show that this decoder can save 30% memory read and write operations in comparison with traditional decoder. Meanwhile, it can reduce 14.5~18% processing time. Finally, we have designed this new LDPC decoder by TSMC .18μm 1P6M process. And chip size including I/O PAD is 1.94x1.94mm2.
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