Chip Design for LDPC decoder employing New Log Domain Algorithm
碩士 === 國立臺北科技大學 === 電子電腦與通訊產業研發碩士專班 === 95 === In this thesis ,we propose a new VLSI architecture for high speed Low Density Parity Check Code decode. A new log domain algorithm is developed for LDPC decoding without losing error correction performance. In comparison with traditional LDPC, this algo...
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ndltd-TW-095TIT056500202019-06-27T05:10:13Z http://ndltd.ncl.edu.tw/handle/zcj3h6 Chip Design for LDPC decoder employing New Log Domain Algorithm 低密度奇偶檢查碼之新型對數域演算法及解碼晶片設計 Zi-Hao Wu 吳子豪 碩士 國立臺北科技大學 電子電腦與通訊產業研發碩士專班 95 In this thesis ,we propose a new VLSI architecture for high speed Low Density Parity Check Code decode. A new log domain algorithm is developed for LDPC decoding without losing error correction performance. In comparison with traditional LDPC, this algorithm can decode the LDPC without saving and reading the value. Thus, we can simplify the decoding flow and increase the decoding throughput. For hardware implementation, we use Xilinx Vertix-4 FPGA to verify this new LDPC decoder firstly. Then we also design this chip by standard cell-based flow. Experiments show that this decoder can save 30% memory read and write operations in comparison with traditional decoder. Meanwhile, it can reduce 14.5~18% processing time. Finally, we have designed this new LDPC decoder by TSMC .18μm 1P6M process. And chip size including I/O PAD is 1.94x1.94mm2. Wen-Ta Lee 李文達 2007 學位論文 ; thesis 58 zh-TW |
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碩士 === 國立臺北科技大學 === 電子電腦與通訊產業研發碩士專班 === 95 === In this thesis ,we propose a new VLSI architecture for high speed Low Density Parity Check Code decode. A new log domain algorithm is developed for LDPC decoding without losing error correction performance. In comparison with traditional LDPC, this algorithm can decode the LDPC without saving and reading the value. Thus, we can simplify the decoding flow and increase the decoding throughput. For hardware implementation, we use Xilinx Vertix-4 FPGA to verify this new LDPC decoder firstly. Then we also design this chip by standard cell-based flow. Experiments show that this decoder can save 30% memory read and write operations in comparison with traditional decoder. Meanwhile, it can reduce 14.5~18% processing time. Finally, we have designed this new LDPC decoder by TSMC .18μm 1P6M process. And chip size including I/O PAD is 1.94x1.94mm2.
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Wen-Ta Lee |
author_facet |
Wen-Ta Lee Zi-Hao Wu 吳子豪 |
author |
Zi-Hao Wu 吳子豪 |
spellingShingle |
Zi-Hao Wu 吳子豪 Chip Design for LDPC decoder employing New Log Domain Algorithm |
author_sort |
Zi-Hao Wu |
title |
Chip Design for LDPC decoder employing New Log Domain Algorithm |
title_short |
Chip Design for LDPC decoder employing New Log Domain Algorithm |
title_full |
Chip Design for LDPC decoder employing New Log Domain Algorithm |
title_fullStr |
Chip Design for LDPC decoder employing New Log Domain Algorithm |
title_full_unstemmed |
Chip Design for LDPC decoder employing New Log Domain Algorithm |
title_sort |
chip design for ldpc decoder employing new log domain algorithm |
publishDate |
2007 |
url |
http://ndltd.ncl.edu.tw/handle/zcj3h6 |
work_keys_str_mv |
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