Chip Design of share Horizontal and Vertical folding structure for LDPC Decoder
碩士 === 國立臺北科技大學 === 電腦與通訊研究所 === 95 === In this thesis, a low hardware cost of VLSI architecture design for Low Density Parity Check(LDPC) Decoder is proposed. Traditional LDPC decoder need horizontal and vertical processorS, In our design, we develop a horizontal and vertical folding structure for...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/zkf5eb |