Design of a Fast-Locking DLL-Based Frequency Multiplier for Wide-Range Operation
碩士 === 淡江大學 === 電機工程學系碩士班 === 95 === The multiphase clocks are usually required in a system-on-chip design. The phase-locked loop (PLL) provides a well locking loop for the synchronization of clocks. However, the inherent high-order loop in the PLL and the jitter accumulation of the VCO make it diff...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/65810126883391966465 |